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Features
* Serial Peripheral Interface (SPI) Compatible * Supports SPI Modes 0 (0,0) and 3 (1,1)
- Datasheet describes Mode 0 Operation
* 50 MHz Clock Rate * Byte Mode and Page Mode Program (1 to 256 Bytes) Operations * Sector/Block/Page Architecture
- 256 byte Pages per Sector - Eight 4 Kbyte Sectors per Block - Four uniform 32 Kbyte Blocks Self-timed Sector, Block and Chip Erase Product Identification Mode with JEDEC Standard Low-voltage Operation - 2.7V (VCC = 2.7V to 3.6V) Hardware and Software Write Protection - Device protection with Write Protect (WP) Pin - Write Enable and Write Disable Instructions - Software Write Protection: * Upper 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array Flexible Op Codes for Maximum Compatibility Self-timed Program Cycle - 30 s/Byte Typical Single Cycle Reprogramming (Erase and Program) for Status Register High Reliability - Endurance: 10,000 Write Cycles Typical 8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP) Die Sales: Waffer Form, Tape and Reel, and Bumped Waffers
* * * *
High Speed Small Sectored SPI Flash Memory
1M (131,072 x 8)
* * * * * *
AT25FS010
Description
The AT25FS010 provides 1,048,576 bits of serial reprogrammable Flash memory organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25FS010 is available in a space-saving 8-lead JEDEC SOIC and 8-lead Ultra Thin SAP packages. Table 0-1.
Pin Name CS SCK SI SO GND VCC WP HOLD
Pin Configuration
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
8-lead JEDEC SOIC
CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
8-lead SAP
___
VCC _____ 8 1 CS 2 ___ SO 3 WP 4 GND
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HOLD 7 SCK 6 SI 5
Bottom View
The AT25FS010 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for upper 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
Operating Temperature....................................-40C to +85C Storage Temperature .....................................-65C to +150C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +5.0V Maximum Operating Voltage ............................................ 4.2V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1-1.
Block Diagram
131,072 x 8
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Table 1-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +3.6V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 1-2. DC Characteristics (Preliminary - Subject to Change) Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +2.7V to +3.6V, TAC = 0C to +70C, VCC = +2.7V to +3.6V (unless otherwise noted)
Symbol VCC ICC1 ICC2 ISB IIL IOL VIL(1) VIH
(1)
Parameter Supply Voltage Supply Current Supply Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage
Test Condition
Min 2.7
Typ
Max 3.6
Units V mA mA A A A V V V V
VCC = 3.6V at 20 MHz, SO = Open Read VCC = 3.6V at 20 MHz, SO = Open Write VCC = 2.7V, CS = VCC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0C to 70C -3.0 -3.0 -0.6 VCC x 0.7 2.7V VCC 3.6V IOL = 0.15 mA VCC - 0.2
10.0 15.0 2.0
17.0 45.0 10.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.2
VOL VOH Note:
Output High Voltage IOH = -100 A 1. VIL and VIH max are reference only and are not tested.
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Table 1-3. AC Characteristics (Preliminary - Subject to Change) Applicable over recommended operating range from TA = -40C to +85C, VCC = +2.7V to +3.6V CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tse tbe tce tSR tBPC Endurance Notes:
(2)
Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Sector Erase Time Block Erase Time Chip Erase Time Status Register Write Cycle Time Byte Program Cycle Time
(1)
Min 0
Typ
Max 50 5 5
Units MHz ns ns ns ns ns ns ns ns ns ns ns
9 9 100 5 5 5 5 5 5 9 0 9 9 9 50 200 1.6 200 500 4 60 30 10K 50
ns ns ns ns ns ms ms s ms s Write Cycles(3)
1. The programming time for n bytes will be equal to n x tBPC. 2. This parameter is ensured by characterization at 3.0v, 25c only. 3. One write cycle consists of erasing a sector, followed by programming the same sector.
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2. Serial Interface Description
MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25FS010 always operates as a slave. TRANSMITTER/RECEIVER: The AT25FS010 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25FS010, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25FS010 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25FS010. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The AT25FS010 has a write lockout feature that can be activated by asserting the write protect pin (WP). When the lockout feature is activated, locked-out sectors will be READ only. The write protect pin will allow normal read/write operations when held high. When the WP is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal status register write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25FS010 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to "1".
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3. Operating Features
3.1 Recommended Power-up
When the power supply is turned on, Vcc rises monotonically from ground to the full operating Vcc. During this time, the Chip Select (CS) signal is not allowed to float and must follow Vcc. For this reason, it is recommended to use a suitable pull-up resistor connected between CS and Vcc. The device is ready for communication once a stable Vcc is reached within the specified operating voltage range.
3.2
Recommended Power-down
The device must be deselected and in Standby and Write Disabled mode prior to Vcc power down sequence. This means there should be no write operation/internal Write cycle or read operation in progress during the Chip Select (CS) line must be allowed to follow Vcc during power down. After power down, it is recommended Vcc should be held at ground level for at least 0.5 seconds before power up again.
3.3
Power On Reset Protection
In order to prevent data corruption and inadvertent Write operations during device power-up and power down, a Power On Reset (POR) circuit is enabled. At Power-up (continuous rise of Vcc from 0v), the device will not respond to any instruction and will be held in reset (which puts the device in standby mode) until the Vcc has reached the Power On Reset threshold voltage. This threshold is lower than the minimum specified Vcc operation voltage. At power down (continuous fall of Vcc), when Vcc drops from the operating voltage below the POR threshold, all operations are disabled and the device will not respond to any command. A stable and valid Vcc must be applied before executing and communication. Please note: The POR threshold trip point is ~1.8v for Serial Flash products and is ensured by design to have a reset during power up and power down and is not 100% tested.
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Figure 3-1. SPI Serial Interface
MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25FS010 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS
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4. Functional Description
The AT25FS010 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25FS010 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 4-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Write is defined as program and/or erase in this specification. The following commands, PROGRAM, SECTOR ERASE, BLOCK ERASE, CHIP ERASE, and WRSR are write instructions for AT25FS010. Table 4-1. Instruction Set for the AT25FS010
One Byte OpCode Binary WREN WRDI RDSR WRSR READ FAST READ PROGRAM SECTOR ERASE (1) BLOCK ERASE(1) 0000 X110 0000 X100 0000 X101 0000 X001 0000 0011 0000 1011 0000 X010 0010 0000 1101 0111 0101 0010 1101 1000 0110 0000 CHIP ERASE(1) 1100 0111 1001 1111 RDID(1) Note: 1010 1011 Hex 06 04 05 01 03 0B 02 20 D7 52 D8 60 C7 9F AB Read Manufacturer and Product ID Erase All Memory Array Erase One 32kbyte Block in Memory Array Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Read Data from Memory Array (with dummy cycles) Program Data Into Memory Array Erase One 4kbyte Sector in Memory Array Operation
Instruction Name
1. Either one of the OP CODES will execute the instruction.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/BUSY and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed.
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These bits are set by using the WRSR instruction. During internal write cycles, all other commands will be ignored except the RDSR instruction. Table 4-2.
Bit 7 WPEN Note:
Status Register Format
Bit 6 BP4 Bit 5 BP3 Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
X = Don't Care
Table 4-3.
Bit Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Bit 4 Bit 5 (BP3) Bit 6 (BP4) Bit 7 (WPEN)
Read Status Register Bit Definition
Definition Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 4-5. See Table 4-5. Not Used See Table 4-5. See Table 4-5. See Table 4-6.
Bits 0-7 are 1s during an internal write cycle.
READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufacturer ID byte followed by two device ID bytes. The manufacturer ID is assigned by JEDEC and is 1Fh for Atmel (see Table 4-4). The first device ID byte indicates the memory type (66h=AT25FS010) followed by the device memory capacity byte (01h). For maximum compatibility and flexibility, two RDID opcodes (9Fh and ABh) are supported and will perform the same operation. Table 4-4. Read Product ID (RDID)
Device ID Memory Type 1Fh 66h Memory Capacity 01h
Manufacturer ID
The device is first selected by driving Chip Select (CS) low then the RDID opcode is shifted in on Serial In (SI) during rising edge of clock. The 24-bit Manufacturer and Device Identification Codes stored in memory are clocked out on Serial Output (SO) starting on the falling edge of clock (see Figure 5-13). If CS stays low after the last bit of second device ID byte is shifted out, the manufacturer ID and 2 byte device ID will continue to be clocked out until CS goes high. The RDID sequence is terminated any time CS is driven high and the device will go into standby mode. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of eight levels of protection for the AT25FS010. The AT25FS010 is divided into eight blocks where the top 1/32, 1/16, 1/8, top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. Any of the locked-out blocks will therefore be READ only. The 9
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locked-out sector/block and the corresponding status register control bits are shown in Table 4-5 on page 10. The six bits, BP0, BP1, BP3, BP4 and WPEN, are nonvolatile cells that have the same properties and functions as the regular memory cells. Table 4-5.
Level BP4 locked Out 0(none) 1(1/32) 2(1/16) 3(1/8) 4(1/4) 5(1/2) 6(ALL) Locked-out Blocks 0 0 1 1 x x x 0 1 0 1 x x x Note: 0 0 0 0 0 1 1 0 0 0 0 1 0 1 None 01F000H - 01FFFFH 01E000H - 01FFFFH 01C000H - 01FFFFH 018000H - 01FFFFH 010000H - 01FFFFH 000000H - 01FFFFH None Sector 8 of Block 4 Sector 7 - 8 of Block 4 Sector 5 - 8 of Block 4 ALL Sectors of Block 4 ALL Sectors of Block 3,4 ALL Sectors of ALL Blocks (1-4)
Sector/Block Write Protect Bits
Status Register Bits BP3 BP1 BP0 Array Address AT25FS010
1. x = don't care
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0." When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the lockedout sectors in the memory array are disabled. Write is only allowed to sectors of the memory which are not locked out. The WRSR instruction is self-timed to automatically erase and program BP0, BP1, BP3, BP4 and WPEN bits. In order to write the status register, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then, CS must be low and the WRSR instruction and data for the six bits are entered. The WRSR write cycle will begin once CS goes high. During the internal write cycle, all instructions will be ignored except RDSR instructions. The AT25FS010 will automatically return to write disable state at the completion of the WRSR cycle. The status register is factory programmed to all 0's.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP pin is held low.
Table 4-6.
WPEN 0 0 1 1 X X X X
WPEN Operation
WP WEN 0 1 0 1 0 1 ProtectedBlocks Protected Protected Protected Protected Protected Protected UnprotectedBlocks Protected Writable Protected Writable Protected Writable Status Register Protected Writable Protected Protected Protected Writable
Low Low High High
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AT25FS010
READ (READ): The READ instruction sequence reads the memory array up to the maximum speed of 50MHz. Reading the AT25FS010 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select the device, the READ instruction is clocked in on the SI line, followed by the byte address to be read. Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line (see Figure 5-6). If only one byte is to be read, the CS line should be driven high after the least significant data bit. To continue read operation and sequentially read subsequent byte addresses from the device by simply keeping CS low and provide a clock signal. The device incorporates an internal address counter that automatically increments to the next byte address during sequential read operation. The READ instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out of the AT25FS010 until the highest byte address is reached. When the last bit of the memory has been read, the device will continue reading back at the beginning of the array (000000h) without delay. The data is always output from the device with the most significant bit (MSB) of a byte first. The READ sequence is terminated any time CS is driven high and the device will go into standby mode. FAST READ (FAST READ): The FAST READ instruction sequence reads the memory array up to the maximum speed of 50MHz (same as standard READ sequence). The FAST READ is an alternate command for the READ and allows for FAST READ instruction compatibility support. The difference between the two is FAST READ requires a "dummy byte" and READ does not. Reading the AT25FS010 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select the device, the FAST READ instruction is clocked in on the SI line, followed by the byte address to be read and the dummy byte (the SO line output will be high Z state). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line (see Figure 5-7). If only one byte is to be read, the CS line should be driven high after the least significant data bit. To continue read operation and sequentially read subsequent byte addresses from the device by simply keeping CS low and provide a clock signal. The device incorporates an internal address counter that automatically increments to the next byte address during sequential read operation. The FAST READ instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out of the AT25FS010 until the highest address is reached. When the last bit of the memory has been read, the device will continue reading back at the beginning of the array (000000h) without delay. The data is always output from the device with the most significant bit (MSB) of a byte first. The FAST READ sequence is terminated any time CS is driven high and the device will go into standby mode. PROGRAM (PROGRAM): The PROGRAM instruction allows up to 256 data bytes to be written to each page in the memory in one-operation changing data bits from a logic 1 to 0 state. The AT25FS010 memory array contains 131,072 programmable data bytes internally organized into 256 bytes per page with a total of 512 pages in the memory. In order to program the AT25FS010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the PROGRAM instruction can be executed and requires the following sequence. After the CS line is pulled low to select the device, the PROGRAM instruction is clocked in via the SI line followed by the byte address (see Figure 5-8) and the data byte(s) to be programmed. Programming will start after CS pin is brought high. Please note: The low to high transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit to initiate programming cycle. Also, a WREN instruction must precede each and every PROGRAM instruction. The Ready/Busy status of the device can be determined by initiating a RDSR instruction. If bit 0=1, the program cycle is
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still in progress. If Bit 0=0, the programming cycle has ended. Only the RDSR instruction is enabled during the programming cycle and all other opcode instructions are ignored until programming cycle has completed. A single PROGRAM instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. The starting byte address can be anywhere within the page. When the end of the page is reached, the address will wrap around to the beginning of the same page. If the data to be programmed is less than a full page, the data of all other bytes on the same page will remain unchanged meaning that the unwritten address locations within the page will not be changed. If more than 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. The same byte cannot be reprogrammed without erasing the whole sector or block first. The AT25FS010 will automatically return to the write disable state at the completion of the programming cycle.
Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state when CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
Table 4-7.
Address Key
Address AN Don't Care Bits AT25FS010 A15 - A0 A23 - A17
ERASE OPERATION: The AT25FS010 memory array is internally organized into uniform 4K byte sectors or uniform 32K byte uniform blocks (see Table 4-8). Before data can be reprogrammed, the sector or block that contains the data must be erased first. In order to erase the AT25FS010, there are three flexible erase instructions that can be executed as follows: SECTOR ERASE, BLOCK ERASE and CHIP ERASE instructions. A SECTOR ERASE instruction allows erasing any individual 4K sector without changing data in rest of memory. The BLOCK ERASE instruction allows erasing any individual block and CHIP ERASE allows erasing the entire memory array. SECTOR ERASE (SECTOR ERASE): The SECTOR ERASE instruction sets all 4K bytes in the selected sector to logic 1 or erased state. In order to sector erase the AT25FS010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE instruction can be executed and will erase every byte in the selected sector if the sector is not locked out. The sector address is automatically determined if any address within the sector is selected (see Figure 5-10). The SECTOR ERASE instruction is internally controlled and self timed to completion. During this time, all commands will be ignored except RDSR instruction. The progress or completion of the erase operation can be determined by reading ready/busy bit (bit 0) through RDSR instruction. If Bit 0=1, sector erase cycle is in progress. If Bit 0=0, the erase operation has been completed. The AT25FS010 will automatically return to the write disable state at the completion of the SECTOR ERASE cycle.
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Table 4-8.
Sector and Block Address
1/32 1/16 Sector 7 1/8 Sector 6 Sector 8 01FFFFH 01F000H 01EFFFH 01E000H 01DFFFH 01D000H 01CFFFH 01C000H 01BFFFH 01B000H 01AFFFH 01A000H 019FFFH 019000H 018FFFH 018000H 017FFFH 010000H 00FFFFH 008000H 007FFFH 000000H
Block 4 1/4
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Block 3
Block 2
Block 1
BLOCK ERASE (BLOCK ERASE): The BLOCK ERASE instruction sets all 32K bytes in the selected block to logic 1 or erased state. In order to block erase the AT25FS010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the BLOCK ERASE instruction can be executed and will erase every byte in the selected block if the block is not locked out. The block address is automatically determined if any address within the block is selected (see Figure 5-11). The BLOCK ERASE instruction is internally controlled and self timed to completion. During this time, all commands will be ignored except RDSR instruction. The progress or completion of the erase operation can be determined by reading ready/busy bit (bit 0) through RDSR instruction. If Bit 0=1, block erase cycle is in progress. If Bit0=0, the erase operation has been completed. The AT25FS010 will automatically return to the write disable state at the completion of the BLOCK ERASE cycle. CHIP ERASE (CHIP ERASE): As an alternative to the SECTOR ERASE/BLOCK ERASE, the CHIP ERASE instruction will erase every byte in all sectors that are not locked out. First, the device must be write enabled via the WREN instruction. Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will automatically be timed to completion. The CHIP ERASE cycle time typically is 8 seconds. During the internal erase 13
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cycle, all instructions will be ignored except RDSR. The AT25FS010 will automatically return to the write disable state at the completion of the CHIP ERASE cycle.
5. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 5-1. Synchronous Data Timing
VIH
t CS
CS
VIL
t CSS t CSH
SCK
VIH
t WH t WL
VIL
t SU
tH
VIH
SI
VALID IN
VIL
tV t HO t DIS
VOH
SO
Figure 5-2.
CS
HI-Z
HI-Z
VOL
WREN Timing
0 SCK
1
2
3
4
5
6
7
SI
WREN OP-CODE
SO
HI-Z
Figure 5-3.
WRDI Timing
CS
SCK
SI
WRDI OP-CODE
SO
HI-Z
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Figure 5-4. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
RDSR OP-CODE
SO
HIGH IMPEDANCE 7
MSB
DATA OUT
6
5
4
3
2
1
0
Figure 5-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
DATA IN
SI
WRSP OP-CODE
7
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Figure 5-6.
CS
READ Timing
0 SCK
1
2
3
4
5
6
7
8
9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 ...
OPCODE SI 0
MSB
ADDRESS BITS A23 - A0 0 1 1 A A A A A A ... A A
MSB
0
0
0
0
A
SO
HIGH IMPEDANCE
DDDDDDDDDD
MSB MSB
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Figure 5-7.
CS
FAST READ Timing
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ...
OPCODE
ADDRESS BITS A23 - A0
DON'T CARE
SI
0 0 0 0 1 0 1 1 A A A A A A ... A A A X X X X X X X X MSB MSB MSB DATA BYTE 1
SO
HIGH IMPEDANCE DDDDDDDDDD MSB MSB
Figure 5-8.
PROGRAM Timing
CS
2075 2076 2077 2078
1
0
1
2
3
4
5
6
7
8
9 10 11 28 29 30 31 32 33 34
SCK
1st BYTE DATA-IN 3-BYTE ADDRESS 256th BYTE DATA-IN
0
SI
PROGRAM OP-CODE
23 22 21
3
2
1
0
7
6
5
4
3
2
SO
HIGH IMPEDANCE
Figure 5-9.
CS
HOLD Timing
t CD t CD
SCK
t HD
HOLD
t HZ
t HD
SO
t LZ
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2079
AT25FS010
Figure 5-10. SECTOR ERASE Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
28
29
30
31
SCK
3-BYTE ADDRESS
SI
SECTOR ERASE OP_CODE
23
22
21
3
2
1
0
SO
HIGH IMPEDANCE
Figure 5-11. BLOCK ERASE Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
28
29
30
31
SCK
3-BYTE ADDRESS
SI
BLOCK ERASE OP-CODE
23
22
21
3
2
1
0
SO
HIGH IMPEDANCE
Figure 5-12. CHIP ERASE Timing
CS
0
1
2
3
4
5
6
7
SCK
SI
CHIP ERASE OP-CODE
SO
HIGH IMPEDANCE
17
5167E-SFLSH-5/09
Figure 5-13. RDID Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
SCK
SI
RDID OP-CODE
DATA OUT
SO
HIGH IMPEDANCE
Manufacturer Code (Atmel = 1Fh)
15 14
3
2
1
0
DEVICE IDENTIFICATION
18
AT25FS010
5167E-SFLSH-5/09
AT25FS010
Ordering Information
Ordering Code AT25FS010N-SH27-B AT25FS010N-SH27-T
(1) (2) (2)
Package 8S1 8S1 8Y7
Operation Range Lead-Free/Halogen-Free/ NiPdAu Lead Finish Industrial Temperature (-40C to 85C)
AT25FS010Y7-YH27-T Notes:
1. "-B" designates bulk ordering code. 2. "-T" designates tape and reel ordering code. SOIC=4K per reel and SAP=3K per reel.
Package Type 8S1 8Y7 8-lead, 0.150" Wide, Plastic Gull Wing Small outline (JEDEC SOIC) 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) Options -2.7 Low Voltage (2.7V to 3.6V)
19
5167E-SFLSH-5/09
6. Part marking scheme
6.1 8-SOIC
Seal Year | Seal Week Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark
TOP MARK
| | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| S 1 3 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot)
6.2
8-Ultra Thin SAP
Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| S 1 3 |---|---|---|---|---|---|---|---| Lot Number |---|---|---|---|---|---|---|---| * | Pin 1 Indicator (Dot) Y= 6: 7: 8: 9: SEAL YEAR 2006 0: 2010 2007 1: 2011 2008 2: 2012 2009 3: 2013 WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 52 = Week 52
TOP MARK
BOTTOM MARK No Bottom Mark
20
AT25FS010
5167E-SFLSH-5/09
AT25FS010
7. Package Information 8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A A1 b C COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE
D
D E1
SIDE VIEW
E e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C
R
21
5167E-SFLSH-5/09
8Y7 - SAP
PIN 1 INDEX AREA
A
PIN 1 ID
D E1
D1
L
E A
A1
b
e e1
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
MIN - 0.00 5.80 4.70 3.30 3.90 0.35
NOM - - 6.00 4.90 3.40 4.00 0.40 1.27 TYP 3.81 REF
MAX 0.60 0.05 6.20 5.10 3.50 4.10 0.45
NOTE
A A1 D E D1 E1 b e e1 L
0.50
0.60
0.70
10/13/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array Package (UTSAP) Y7 DRAWING NO. 8Y7 REV. B
R
22
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AT25FS010
8. Revision History
Doc. Rev. 5167E
Date 5/2009
Comments Corrected Block Diagram Memory Array Added Die Sales Info to Features Added lines to Ordering Codes table Updated to new Template Added Part Marking tables Changed `Advance Information' to Preliminary Changed `BLOCK ERASE(1)' operation from 64kbyte to 32kbyte on page 7. Initial document release.
5167D
8/2007
5167C 5167B 5167A
4/2007 1/2007 8/2006
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5167E-SFLSH-5/09
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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5167E-SFLSH-5/09

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